1. Field of the Invention
The present invention relates to a semiconductor device, such as a DRAM (Dynamic Random Access Memory), and in particular to a memory device having a booster circuit that supplies a selection level for a word line, and to a control method for a booster circuit.
2. Related Arts
For a conventional semiconductor memory device, such as a DRAM, memory cells having a single selection transistor and a capacitor for storing memory data are provided at each intersection of a word line and a bit line. A selected word line is activated at a selected high level, a selected transistor is rendered on, the level of a bit line is changed in accordance with whether or not electric charges have been accumulated in the capacitor, and a sense amplifier circuit connected to the bit line reads the slight change in the bit line.
For the normal operation of the DRAM, a pre-charge period, during which the level of a bit line, etc., is pre-charged, and an active period, during which the word line is activated as described above and data in the memory cells are read, are alternately repeated.
In accordance with the increase in the capacity of the memory device, the volume of the electric charge accumulated in the capacitor of the memory cell is reduced compared with the capacity of the bit line. In order to ensure that data can be read, the selection level of a selected word line is set to be higher than a power source voltage. Therefore, a booster circuit is provided which supplies the voltage higher than the power source voltage to a word line driver circuit connected to the word line.
In FIG. 6, a timing chart for a DRAM is used for explaining the operation of such a booster circuit. In the booster circuit, generally, a pumping pulse (boosting pulse) from an oscillator, such as a ring oscillator, is applied to one of the electrodes of the capacitor in the booster circuit, so as to boost the output voltage at the other electrode. Further, in order to save the power consumption, the boosting pulse is supplied to the booster circuit for performing the boosting operation only during the active period while the word line is activated. Usually, the active period is controlled by a /RAS (RAS bar) signal, which is an inversion of an RAS (Row Address Strobe) signal. In other words, the period corresponding to the emission of the low-level /RAS signal, during which a valid Row address signals are supplied, is the active period, while the period corresponding to the emission of a high-level /RAS signal is the pre-charge period.
As is shown in FIG. 6, as the selected word line WL rises, voltage Vpp at a boosting level is first dropped, and is then returned by the boosting pulse so as to prepare for the succeeding active period.
However, in accordance with the recent increase in the memory capacities, the number of memory cells connected to a single word line has increased, and in addition, as the word lines become minute, the parasitic capacity of an individual word line has become larger. Thus, since a reduction in the voltage Vpp at the boosting level that is to be supplied from the boosting circuit to the selected word line tends to be greater (Vpp2 in FIG. 6), the boosting load is increased. In addition, since a shorter cycle is required in accordance with the higher memory speed, the active period is shortened. As a result, for the boosting operation during the active period in the conventional manner, level Vpp3 can not be returned to the original level Vpp1, and in the active period of the next cycle, the voltage level available for a selected word line is reduced to Vpp4, so that it is not possible to adequately read data in the memory cell.
To resolve these shortcomings, it could be proposed that the capacity of a ballast capacitor at the output section of a booster circuit be increased, and that the capacity of the capacitor of the booster circuit be increased to enhance the ability of the boosting circuit. However, neither solution is the preferable one because these solution yield larger dimensions of the capacitors which will not matches the requirement of the large capacity and high integration for the semiconductor memory.
It is, therefore, one object of the present invention to provide a memory device having a boosting circuit that can fully recover the level of the boosting voltage supplied to the selected word line.
It is another object of the present invention to provide a memory device having an improved booster circuit with matching an increase of memory capacity, so that a level for a selected word line can be maintained high enough for adequately reading data.
It is an additional object of the present invention to provide a memory device that, without requiring a drastic increase in the consumed power, can prevent a reduction in a voltage level of a selected word line by enhancing the boosting operation of a booster circuit.